The present invention relates to an operating method of a flash memory device, and more particularly, to a program verifying method of a NAND flash memory device and a programming method using the same.
Recently, there is a high demand for flash memory devices that are electrically programmable/erasable but do not require a refresh operation for rewriting data at regular periods. There has been a great effort to develop high-capacity flash memory devices capable of storing a large volume of data.
In this regards, a NAND flash memory device which includes a plurality of memory cells connected in series to form one string for achieving high degree of integration, are widely used. To increase storage capacity while reducing chip size, multi-level cell (MLC) devices that can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells are introduced. A multi-level cell can store two or more bits of information while a single level cell (SLC) can store only one bit of information, for example, a programmed state and an erased state. Therefore, the storage capacity of the MLC flash memory device is twice or more greater than that of the SLC flash memory device. Typically, the MLC has two or more threshold voltage distributions, and thus has two or more data storage states corresponding thereto.
A program operation of the MLC flash memory device is performed on a page basis. As a word line bias voltage for programming is applied to a word line connected to MLCs of a selected page, the MLCs are programmed. Recently, to increase the program speed of the MLC flash memory device, an incremental step pulse programming (ISPP) method of programming a selected page while incrementally increasing the word line bias voltage has been employed.
FIG. 1 illustrates threshold voltage distributions of a NAND flash memory device with a 2-bit MLC.
Referring to FIG. 1, in the MLC flash memory device where 2-bit data can be programmed in one memory cell, there are four possible data storage states(i.e., [11], [10], [01] and [00]), each corresponding to a threshold voltage distribution of the MLC. Typically, in the program process of the MLC flash memory device, the threshold voltage of a MLC is changed to a voltage associated with a data value to be stored. Each memory cell of the MLC flash memory device has a threshold voltage distribution 110 corresponding to an erased state (hereinafter, referred to as erased threshold voltage distribution for simplicity), and threshold voltage distributions 120, 130 and 140 corresponding to a plurality of programmed states (hereinafter, referred to as programmed threshold voltage distribution for simplicity). The programmed threshold voltage distributions 120, 130 and 140 are distinguished from the erased threshold voltage distribution 110 which is a first read voltage Vread0 (generally, 0 V). The programmed threshold voltage distributions 120, 130 and 140 are distinguished from each other by a second read voltage Vread1 a third read voltage Vread2, and a forth read voltage Vread4 respectively.
A fast programming speed of a memory device and a reduction in width of a distribution of a threshold voltage of a memory cell are considered very important in both SLC and MLC flash memory devices. As the MLC flash memory will be developed to have more dense cell configuration, from a current 4-level MLC to an 8 or more-level MLC, reducing the width of distribution of each threshold voltage of a memory cell will be more critical issues.
The programmed threshold voltage distributions 120, 130 and 140 are represented between the first read voltage Vread0 to a pass voltage Vpass in the MLC flash memory device. If the width of the threshold voltage distribution is reduced, the number of bits storable in one memory cell also increases, and thus larger volume of data can be stored in the flash memory device. Therefore, it is beneficial if the threshold voltage distribution is narrowed in the MLC flash memory device.
Since a conventional programming method of an MLC flash memory device employs the incremental step pulse program (ISSP) method, a method of reducing the magnitude of the step voltage can be used to reduce the width of distribution of threshold voltages. However, it is hard to reduce the magnitude of the step voltage unlimitedly because the reduction of the step pulse causes more program pulses and thus increases a programming time. Accordingly, it is necessary to develop a method that can effectively reduce the width of a threshold voltage distribution of a memory cell while not increasing a programming time in the memory cell.